The present invention relates to a variable frequency filter circuit for use, suitably as a base band LPF circuit, in an RF front-end section of a digital satellite broadcasting receiver of a direct conversion type, in which a received high-frequency signal is directly demodulated into a base band signal.
In case an above-described digital satellite-broadcasting receiver is realized adopting a direct conversion method, it is necessary for a base band LPF (Low Pass Filter) to have a band sufficient for passing a data rate of a received signal, because an output from mixer is directly separated into desired quadrature modulation signals I and Q. On the other hand, as a band of a broadcasting signal is compressed while receiving channels are increased in number, it becomes more important to have a higher interference characteristic against an adjacent signal. In view of this, higher cut-off frequency accuracy ensures an amount of attenuation against adjacent channel interference, thereby improving reception quality (bit error rate). For this reason, the base band LPF circuit needs to accurately adjust a cut-off frequency in order to attenuate the adjacent signal by a sufficient amount within a most suitable bandwidth according to the data rate of the received signal.
FIG. 10 is a block diagram illustrating an electrical arrangement of a typical conventional LPF circuit 1 which is such a cut-off frequency variable LPF circuit realized on an integrated circuit. The LPF circuit 1 is a tertiary LPF. A base band signal from mixer, which is inputted from an input terminal 2, is outputted from an output terminal 3 after passing through an LPF F1 and an LPF F2 connected in series. The LPF F1 has primary cut-off frequency characteristics, whereas the LPF F2 has secondary cut-off frequency characteristics. For example as shown in FIG. 11, the LPF F1 is composed of a gm amplifier A1, and the LPF F2 is composed of gm amplifiers A21 and A22 (hereinafter, the reference mark A is used to refer to all of them), and the LPF F1 is provided with capacitor C1, and the LPF F2 is provided with capacitors C21 and C22. The capacitors C1, C21, and C22 are for determining Q in connection with the respective gm amplifiers A1, A21, and A22.
Each of the gm amplifiers A is, as shown in FIG. 12, can be described as a circuit that is provided with a power supply 11, constant current sources 12 to 15, transistors Q1 to Q6, and an emitter resistance RE.
The power supply 11 steps down a power supply voltage Vcc by a predetermined voltage. The transistor Q1, arranged as a diode with its collector connected with its base, supplies a constant current from the power supply 11. A collector of the transistor Q2 receives an emitter current of the transistor Q1. A base of the transistor Q2 functions as a normal input IN. The transistor Q2 receives a base band signal from the normal Input IN via an input terminal 2. The constant current source 12 pulls out a constant current IA from an emitter of the transistor Q2. The transistors Q1 and Q2, and the constant current source 12 constitute a series circuit.
The transistor Q3, arranged as a diode by connecting its collector with its base, supplies a constant current from the power supply 11. A collector of the transistor Q4 receives an emitter current of the transistor Q3. A base of transistor Q4 functions as an inverting input XIN. A later-described output signal OUT is negatively fed back the inverting input XIN. The constant current source pulls out a constant current IA from an emitter of the transistor Q4. The transistors Q3 and Q4, and the constant current source 13 constitute a series circuit similar to the above-described series circuit.
The emitter resistance RE is a resistance that connects the emitter of the transistor Q2 and the emitter of the transistor Q4. Bases of the transistors Q5 and Q6 in pair respectively receive collector voltages of the transistors Q2 and Q4. The output voltage OUT is derived from a collector of the transistor Q5, and negatively fed back into the base of the transistor Q4. The constant current source 14 pulls out a constant current IB mutually from emitters of the transistors Q5 and Q6. The constant current source 15 supplies a constant current IB/2 to the collector of the transistor Q5.
Gains, gms, of the gm amplifiers A having the above arrangement can be represented by the following equation:                               gm          =                      1                          {                                                (                                      RE                    +                                                                  2                        ·                        Vt                                                                    I                        A                                                                              )                                ·                                  (                                                            I                      B                                                              2                      ·                                              I                        A                                                                              )                                            }                                      ,                  Vt          =                      kT            q                                              (        1        )            
where IA and IB are current values of the constant rent sources, RE is an emitter resistance value, k is the Boltzmann""s constant (1.38xc3x9710xe2x88x9223), T is an absolute temperature (K), and q is an electrical charge of one electron (1.6xc3x9710xe2x88x9219).
Cut-off frequencies xcfx891 and xcfx892 of the LPFs F1 and F2 using the gm amplifiers A are represented as follows:                                           ω            ⁢            1                    =                                    gm              ⁢                              xe2x80x83                            ⁢              1                                      C              ⁢              1                                      ⁢                  
                                    (        2        )                                          ω          ⁢          2                =                                            gm              ⁢                              xe2x80x83                            ⁢                              21                ·                gm                            ⁢                              xe2x80x83                            ⁢              22                                      C              ⁢                              xe2x80x83                            ⁢                              21                ·                C                            ⁢                              xe2x80x83                            ⁢              22                                                          (        3        )            
where gm1 is a gm of the am amplifier A1, gm 21 is a gm of the gm amplifier A21, and gm 22 is a gm of the gm amplifier A22.
Here, the cut-off frequency xcfx891 of the LPF F1 is in proportion with the gm 1, and the cut-off frequency xcfx892 of the LPF F2 is in proportion with gm 21 and gm 22. Meanwhile, the gm 1, the gm 21, and the gm 22 are in proportion with 1/IB. Therefore, when a value of the constant current IB is halved, the cut-off frequencies xcfx891 and xcfx892 are doubled. Thus, accurate control of the constant current IB enables accurate adjustment (varying) of the cut-off frequencies xcfx891 and xcfx892. In response to cut-off frequency selection signals S1 and S2 inputted into a signal input terminal 4, the value of the constant current IB is controlled by current value converting circuits B1 and B2 provided respectively in the LPF F1 and LPF F2. The current value converting circuits B1 and B2 respectively control the constant current IB as reference currents IB1 and IB2.
The LPF circuit 1 shown in FIG. 10 is provided with a reference LPF F2a (an LPF F2a for reference), an input amplifier 5, a phase comparator 6, a high gain voltage amplifier 7, a voltage-current converting circuit 8, and constant current sources 9 and 10, in order to control the value of the constant current IB accurately.
The input amplifier 5 adjusts a level of a reference frequency signal xcfx890 inputted from an input terminal 2a. The phase comparator 6 detects a phase difference between (1) the reference frequency signal xcfx890 whose level has been adjusted by the input amplifier 5, and (2) an output signal of the LPF F2a. The high gain voltage amplifier 7 amplifies the compared output signal, thereby ensuring sensitivity for the phase difference around 90xc2x0. The voltage-current converting circuit 8 converts, into a current value, a voltage value that is outputted from the high gain voltage amplifier 7, then extracts the current value as a reference current I0 for a current mirror circuit. The constant current sources 9 and 10 respectively generate constant currents IB2a and IB12 in accordance with the reference current I0, and supply the constant currents IB2a and IB12 to the reference LPF F2a and the current value converting circuits B1 and B2.
The reference LPF F2a is a secondary LPF identical to the secondary LPF F2, which is an LPF of a main body, in terms of a circuit arrangement and a circuit element constant, so as to take an advantage of having, as shown in FIG. 13, a 90xc2x0 phage difference between the input signal and the output signal for the cut-off frequency xcfx890 at which a frequency property is dropped by xe2x88x923 dB, thereby avoiding unevenness in absolute output values with respect to a relationship between (a) an input phase difference for the phase comparator 6 and (b) a compared output. Further, as shown in FIG. 14, when the phase difference is 90xc2x0, the output voltage of the high gain voltage amplifier 7, which amplifies an output level of the phase comparator 6, is 0V. Thus, in a vicinity of 90xc2x0, the output voltage is largely varied in response to a slight change in the phase difference. In other words, the high gain voltage amplifier 7 operates with a high gain.
Put as a reference is the reference current I0 acquired by performing the voltage-current conversion of the output signal level of the high gain voltage amplifier 7 by the voltage-current converting circuit 8. Having the reference current I0 as the reference, the constant current value IB2a, which is generated by the current mirror circuit built in the constant current source 9, is supplied to the reference LPF F2a. In this way, the phase difference of the input/output signals of the reference LPF F2a is controlled so as to be 90xc2x0, in other words, so that the output signal level of the high gain voltage amplifier 7 will be 0V. As a result, the cut-off frequency xcfx892a of the reference LPF F2a is adjusted to a frequency of the reference frequency signal xcfx890.
Having the reference current I0 as reference, the constant current source 10 outputs the constant current IB12 for generation of the reference currents IB1 and IB2 that are for adjusting the cut-off frequencies of the LPFs F1 and F2. In case the cut-off frequencies xcfx891 and xcfx892 of the LPFs F1 and F2 are to be adjusted to desired frequencies, the frequency of the reference frequency signal xcfx890 is directly changed so as to adjust the cut-off frequencies xcfx891 and xcfx892 to the desired frequencies. However, there is a possibility that a fundamental wave and a higher harmonic wave of the reference frequency xcfx890 may interfere the base band signal. Therefore, the reference current IB1 of the gm amplifier A1, and the reference current IB2 of the gm amplifiers A21 and A22 are generated, in accordance with the constant current IB12, by the current value converting circuits B1 and B2 constituted of current mirror circuits as shown in FIG. 15. The reference current IB1 and the constant IB12 determine the cut-off frequencies.
The current value converting circuits B1 and B2 are provided with four transistors Q11 to Q14, switches SW1 to SW4, and a current source control circuit 16.
The transistors Q11 to Q14 are positioned in parallel to each other in such a manner that elements of the transistors Q11 to Q14 are in a ratio of 1:2:4:8 in terms of numbers, the elements being of the same characteristics. Bases of the transistors Q11 to Q14 mutually receive the constant current IB12, and collectors of the transistor Q11 to Q14, which are connected to each other, output the reference currents IB1 and IB2.
The switches SW1 to SW4 connect emitters of the transistors Q11 to Q14 respectively to GND. The current source control circuit 16 performs ON/OFF control of the respective switches SW1 to SW4.
The current source control circuit 16 selectively turns one of the switches SW1 to SW4, in response to cut-off frequency selection signals S1 and S2 in two bits, which is inputted to the input terminal 4. Thereby, the current source control circuit 16 can vary the reference currents IB1 and IB2 to two, four, and eight times of a current flowing through the transistor Q11. A value of the constant current IB12 of the constant current source 10 is so set that the reference current IB2 of the current value converting circuit B2 will be at the same value as the reference current IB2a of the reference LPF F2a when the transistor Q14 is turned ON. In this way, as shown in Table 1, realized is the LPF circuit 1 capable of selecting four (4) kinds of cut-off frequencies xcfx891 and xcfx892 by switching over the cut-off frequencies selection signals S1 and S2 in accordance with the received signal.
Furthermore, the reference frequencies xcfx890 for determining the cut-off frequencies xcfx891 and xcfx892 is adjusted by varying a ratio between the current values IB2a and IB12 outputted respectively from the constant current sources 9 and 10. Thus, the a range of the adjustment and a setting of the adjustment as to stages can be adjusted by incorporating the current value converting circuits B1 and B2 with this arrangement.
The LPF circuit 1 having the above arrangement is so adopted that the thus set cut-off frequencies can be adjusted by the current value converting circuits B1 and B2 in response to such influence given by a power supply voltage, ambient temperatures, or unevenness as to circuit layouts, so that the accuracy of the cut-off frequency selection signals S1 and S2 can be maintained even though there is such influence. Moreover, because the LPFs F1 and F2 operate all the time, such adjustment of the cut-off frequencies is carried out by using the reference LPF F2a or the like that has the same characteristics as the LPFs F1 and F2 of the main body, so as not to retard a flow of the base band signal.
Then, the reference LPF F2a receives, instead of the received base band signal, the reference frequency signal xcfx890 whose frequency is highly accurate. The cut-off frequency selection signals S1 and S2 are adjusted so that the phase difference between that reference frequency signal xcfx890 and the output signal of the reference LPF F2a will be constant. Because of this, the reference LPF F2a has a cut-off frequency that is highly accurate almost as that of the reference frequency signal xcfx890, thereby ensuring that the reference LPF F2a is highly accurate.
This arrangement has no problem as long as the LPFs F1 and F2 of the main body, and the reference LPF F2a have perfectly identical characteristics. However, there are two types of causes for unevenness in elemental characteristics of integrated circuits, namely, (1) characteristic variations (absolute unevenness) between a plurality of the integrated circuits formed on a semiconductor wafer, and (2) characteristic variations (relative unevenness) due to the circuit layouts which are caused, even in one integrated circuit, because of a location in which the circuit element is mounted, a direction in which the circuit element is positioned, or the like cause. The absolute unevenness, the former, can be avoided in the conventional adjusting method by having an identical circuit arrangement and constant elemental number for the LPFs F1 and F2 of the main body, and the reference LPF F2a. However, the conventional adjusting method has such a problem that the relative unevenness, the later, cannot be avoided in the conventional adjusting method, because the two LPFs F1 and F2, and the LPF F2a are independent of each other.
Specifically, an effect of the relative unevenness can be diminished by having a special circuit layout. For example, regarding the resistance, the circuit layout may be so arranged that the resistance is constituted of a plurality of the resistance elements connected in series-parallel, instead of using one resistance element to achieve the desired value of the resistance. However, it is quite disadvantageous in terms of area to have such circuit layout in which the relative unevenness among the LPFs F1 and F2, and the reference LPF F2a is considered, in addition to the arrangement in which the two LPFs, namely the LPFs F1 and F2 are provided in the main body for the I signal and for the Q signal, with an extra circuit, namely the reference LPF F2a, provided therewith.
Furthermore, in the adjusting method of the cut-off frequency, the arrangement for adjusting the reference LPF F2a and the like operates all the time during the reception of the satellite broadcasting, regardless whether the cause of the variations, such as the power supply voltage or the ambient temperatures, is present or absent. Because of this, it is necessary to have consideration in terms of the circuit arrangement and wiring, lest the reference frequency signal xcfx890, which has the same frequency band and the received signal, bypasses the reference LPF F2a and reaches to the base band amplifier of a next stage. It is a problem that this affects a layout of the whole integrated circuit.
The present invention has an object of providing a variable frequency filter circuit capable of suppressing an effect caused by an arrangement for adjusting a cut-off frequency.
A variable frequency filter circuit of the present invention, in order to attain the above object, is provided with (1) a filter for adjusting a cut-off frequency, (2) an adjusting section for arbitrarily setting the cut-off frequency of the filter in accordance with a variable setting value so at to adjust the cut-off frequency, (3) a first recording section for storing therein a first compensating value for compensating the setting value, the first compensating value being worked out in advance via simulation in order to compensate circuit characteristics that dynamically vary depending on usage, (4) a reference signal source for generating a reference frequency signal, (5) an input switching section, provided in an input stage of the filter, for inputting, to the filter, the reference frequency signal instead of an input signal, during an adjusting mode period during which the adjusting section adjusts the cut-off frequency, (6) a control section for adjusting the setting value so that an output from the filter with respect to the reference frequency signal will have a predetermined value, and for outputting the setting value, and (7) a second recording section for storing the adjusted setting value as a second compensating value, wherein during a regular operation mode period the control section compensates a shift in the cut-off frequency due to a change in the circuit characteristics by compensating the setting value with the first compensating value stored in the first recording section, and compensates a shift in the cut-off frequency due to a circuit layout by compensating the second compensating value stored in the second recording section.
With the above arrangement, where the adjusting mode is provided, the shift of the cut-off frequency is detected and compensated by using the filter for filtering an actual signal. Compared with an arrangement where a reference filter and the like are specially provided for detecting and compensating the shift, the above arrangement suppresses an influence due to relative unevenness of circuit elements as to circuit layouts. Moreover, for a variable frequency filter circuit adopted to suppress the influence given by the arrangement for adjusting the cut-off frequency, such as reduction of current consumed and preventing an interface signal from reaching to a receiving signal, the above arrangement makes it possible to work out, in advance and with accuracy, a shift of the cut-off frequency due to a dynamic change in circuit characteristics of the filter, which is caused by a change in a power supply voltage or an ambient temperature, for example, and which cannot be detected without a special arrangement for detecting the shift of the cut-off frequency. Therefore, a compensating value for compensating the shift is stored in the first recording section as the first compensating value. The setting value previously mentioned can be compensated in accordance with the first compensating value corresponding to the power supply voltage or the ambient temperature actually detected, and the second compensating value corresponding to relative unevenness that is a constant value even though each circuit element has different relative unevenness. Thereby, a shift due to the relative unevenness in the cut-off frequency can be compensated.
This eliminates an influence given by the arrangement for adjusting the cut-off frequency, requires no special consideration for circuit layout and wiring, and reduces time for layout.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.